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    Effects of PEDOT:PSS and crystal violet interface layers on current-voltage performance of Schottky barrier diodes as a function of temperature and variation of diode capacitance with frequency
    (Elsevier, 2022) Deniz, A. R.; Tas, A. I.; Caldiran, Z.; Incekara, U.; Biber, M.; Aydogan, S.; Turut, A.
    In this study, diode applications of Crystal Violet (CV) and PEDOT materials were studied. The Ni/p-Si/Al, Ni/CV/p-Si/Al and Ni/PEDOT:PSS/CV/p-Si/Al diodes were fabricated. The I-V (current-voltage) characteristics of all diodes were analyzed at room temperature, it was determined that the PEDOT:PSS and CV materials improved the basic diode parameters. Also, I-V characteristics of Ni/PEDOT:PSS/CV/p-Si/Al of diode were investigated for different temperature values. It has been determined that the basic diode parameters are strongly dependent on temperature. It was determined that while the barrier height (Fb) increased with increasing temperature, the ideality factor (n) and the series resistance (Rs) values decreased. Using temperature-dependent measurements, it was determined that the potential barrier and ideality factor values at the contact interface has a double Gaussian distribution. In addition, C-V (capacitance-voltage) measurements of these diodes were analyzed depending on the frequency. It was found that the diode capacitance decreased with increasing frequency.
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    The electrical current characteristics of thermally annealed Co/anodic oxide layer/n-GaAs sandwich structures
    (World Scientific Publ Co Pte Ltd, 2019) Yildirm, N.; Turut, A.; Biber, M.; Saglam, M.; Guzeldir, B.
    The Co/anodic oxide layer/n-GaAs MOS structures have been fabricated by us. The MOS structures have shown an excellent rectifying behavior before and after thermal annealing of 500 degrees C for 2 min. It has been stated in the literature that the thermal annealing at a relatively low-temperature can improve the quality and performance of the anodic MOS structure. The current-voltage (I-V) measurements of the annealed MOS structure have been attempted in the measurement temperature range 60-320 K with the steps of 20 K. The I-V plot at 300 K has given the diode parameter values as barrier height (Phi(b0) = 0.96 eV and ideality factor n = 1.22, diode series resistance R-s = 124 Omega for the annealed sample, and (Phi(b0) = 0.87 eV and n = 2.11, R-s = 204 Omega for the nonannealed structure. A mean tunneling potential barrier value of 0.59 eV for the anodic oxide layer at the Co/n-GaAs interface has been calculated from the current- voltage-temperature curves. Furthermore, Phi(b0)(T) versus (2kT)(-1) curve has followed a double Gaussian distribution (GD) of the barrier heights. It has been stated that the double GD may be originated from the presence of the surface patches and phases arisen at the anodic oxide layer/n-GaAs interface.